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RISC-V Nuttx ... SUCCESS!

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  • Ken Pettit
    SUCCESS! On my RISC-V FPGA, I just now achieved: NuttShell (NSH) nsh And I am able to run multiple tasks, at least using a simple test like: nsh time sleep
    Message 1 of 14 , Oct 14, 2016
      SUCCESS!

      On my RISC-V FPGA, I just now achieved:

      NuttShell (NSH)
      nsh>

      And I am able to run multiple tasks, at least using a simple test like:

      nsh> time "sleep 5" &
      nsh> help

      This properly displays the help usage and commands, followed by "5.0100
      sec". Also, I ran the ostest example and it looks like all PASS
      conditions there also. Now for some major cleanup, checking of file
      header comments, and delay loop timing, etc.

      Ken
    • Ramtin Amin
      Congrats !!!! really curious to see the code :p On Saturday, 15 October 2016, Ken Pettit pettitkd@gmail.com [nuttx]
      Message 2 of 14 , Oct 15, 2016
        Congrats !!!!
        really curious to see the code :p

        On Saturday, 15 October 2016, Ken Pettit pettitkd@... [nuttx] <nuttx@yahoogroups.com> wrote:
         

        SUCCESS!

        On my RISC-V FPGA, I just now achieved:

        NuttShell (NSH)
        nsh>

        And I am able to run multiple tasks, at least using a simple test like:

        nsh> time "sleep 5" &
        nsh> help

        This properly displays the help usage and commands, followed by "5.0100
        sec". Also, I ran the ostest example and it looks like all PASS
        conditions there also. Now for some major cleanup, checking of file
        header comments, and delay loop timing, etc.

        Ken

      • Alan Carvalho de Assis
        Congratulations Ken! It is an amazing achievement! BR, Alan On 10/15/16, Ken Pettit pettitkd@gmail.com [nuttx]
        Message 3 of 14 , Oct 15, 2016
          Congratulations Ken!

          It is an amazing achievement!

          BR,

          Alan

          On 10/15/16, Ken Pettit pettitkd@... [nuttx]
          <nuttx@yahoogroups.com> wrote:
          > SUCCESS!
          >
          > On my RISC-V FPGA, I just now achieved:
          >
          > NuttShell (NSH)
          > nsh>
          >
          > And I am able to run multiple tasks, at least using a simple test like:
          >
          > nsh> time "sleep 5" &
          > nsh> help
          >
          > This properly displays the help usage and commands, followed by "5.0100
          > sec". Also, I ran the ostest example and it looks like all PASS
          > conditions there also. Now for some major cleanup, checking of file
          > header comments, and delay loop timing, etc.
          >
          > Ken
          >
        • spudarnia
          Hi, Ken, ... Wow! That seemed like a very fast bring-up. But I bet it was not so fast from your point of view. My Xtensa port is going very slowly. At this
          Message 4 of 14 , Oct 15, 2016
            Hi, Ken,

            > SUCCESS!
            >
            > On my RISC-V FPGA, I just now achieved:
            >
            > NuttShell (NSH)
            > nsh>
            >
            > And I am able to run multiple tasks, at least using a simple test like:
            >
            > nsh> time "sleep 5" &
            > nsh> help

            Wow! That seemed like a very fast bring-up. But I bet it was not so fast from your point of view.

            My Xtensa port is going very slowly. At this rate it will probably take me a month.

            > This properly displays the help usage and commands, followed
            > by "5.0100 sec". ...

            The 0.01 is one clock tick. Sleep always waits one clock tick longer than you request to assure that "at least" the requested time elapses (not at most). The time command also has an error of one clock tick. The real time is some time between 5.0000 and 5.0100.

            > ... Also, I ran the ostest example and it looks like all PASS
            > conditions there also. Now for some major cleanup, checking of file
            > header comments, and delay loop timing, etc.

            The OS test is pretty good for this kind of thing. It really does exercise the core OS logic and certainly means that there are no major errors there.

            I wish I had an easier to access PASS/FAIL indication from ostest. I usually just log the ostest results and do;

            grep -I error ostest.log | grep -v nerrors=0

            There is still some error counters that will be displayed but it is easy to assure that the counts are all zero.

            Greg
          • spudarnia
            For those of you that have expressed an interest, Ken s RISC-V port is now available in the NuttX repository. Ken says that FPGA code will soon follow. Greg
            Message 5 of 14 , Oct 16, 2016
              For those of you that have expressed an interest, Ken's RISC-V port is now available in the NuttX repository. Ken says that FPGA code will soon follow.

              Greg

            • Ramtin Amin
              Wow, great job. thx On Sun, Oct 16, 2016 at 5:55 PM, spudarnia@yahoo.com [nuttx]
              Message 6 of 14 , Oct 16, 2016
                Wow, great job.
                thx


                On Sun, Oct 16, 2016 at 5:55 PM, spudarnia@... [nuttx] <nuttx@yahoogroups.com> wrote:
                 

                For those of you that have expressed an interest, Ken's RISC-V port is now available in the NuttX repository. Ken says that FPGA code will soon follow.

                Greg


              • Ramtin Amin
                hi Ken, I know you derived your nanorv32 from a Picorv32. I managed in the past to use a picorv32 in my soc: https://github.com/cliffordwolf/picorv32/ How far
                Message 7 of 14 , Oct 16, 2016
                  hi Ken,

                  I know you derived your nanorv32 from a Picorv32.

                  I managed in the past to use a picorv32 in my soc: https://github.com/cliffordwolf/picorv32/

                  How far is this picorv32 from your current soc, how much do you think would need to be adapted to get it to work with this ?



                  On Sun, Oct 16, 2016 at 6:05 PM, Ramtin Amin <keytwo@...> wrote:
                  Wow, great job.
                  thx


                  On Sun, Oct 16, 2016 at 5:55 PM, spudarnia@... [nuttx] <nuttx@yahoogroups.com> wrote:
                   

                  For those of you that have expressed an interest, Ken's RISC-V port is now available in the NuttX repository. Ken says that FPGA code will soon follow.

                  Greg



                • spudarnia
                  Crow supply project to develop a RISC-V chip: https://www.crowdsupply.com/onchip/open-v
                  Message 8 of 14 , Nov 23, 2016
                    Crow supply project to develop a RISC-V chip: https://www.crowdsupply.com/onchip/open-v
                  • Ken Pettit
                    Hmm, 8K RAM. Wow, wonder what kind of programs they expect to run with 8K of combined code + data RAM! I think I will spend Friday finishing the cleanup of my
                    Message 9 of 14 , Nov 23, 2016
                      Hmm, 8K RAM.  Wow, wonder what kind of programs they expect to run with 8K of combined code + data RAM!

                      I think I will spend Friday finishing the cleanup of my RISC-V FPGA project (need to pull out a handful of non-releasable items still) and get it posted to the world.  The ASCIs I am developing have more like 256K SRAM for code and 128K for data, but then they are being devloped in 14nm vs 130.

                      Perhaps I should talk to our CEO about doing a 40nm RISC-V Croud source chip that is actually useful for something :)

                      Ken

                      On 11/23/16 3:35 PM, spudarnia@... [nuttx] wrote:
                       

                      Crow supply project to develop a RISC-V chip: https://www.crowdsupply.com/onchip/open-v


                    • spudarnia
                      Yet another Crowd Supply RISC-V project: https://www.crowdsupply.com/sifive/hifive1
                      Message 10 of 14 , Nov 29, 2016
                        Yet another Crowd Supply RISC-V project: https://www.crowdsupply.com/sifive/hifive1
                      • Ken Pettit
                        This would be the first RISC-V chip developed by SiFive I believe. SiFive was founded by the guys from Berkley who created the RISC-V. I have been working with
                        Message 11 of 14 , Nov 29, 2016
                          This would be the first RISC-V chip developed by SiFive I believe.  SiFive was founded by the guys from Berkley who created the RISC-V.  I have been working with them on the RISC-V debug specification a little.

                          Ken

                          On 11/29/16 2:59 PM, spudarnia@... [nuttx] wrote:
                           

                          Yet another Crowd Supply RISC-V project: https://www.crowdsupply.com/sifive/hifive1


                        • franck gastel
                          again I do not get the goal of making an asic out of a risc + a couple of cores. what does it bring ? On Wed, Nov 30, 2016 at 12:08 AM, Ken Pettit
                          Message 12 of 14 , Nov 29, 2016
                            again I do not get the goal of making an asic out of a risc + a couple of cores. what does it bring ?


                            On Wed, Nov 30, 2016 at 12:08 AM, Ken Pettit pettitkd@... [nuttx] <nuttx@yahoogroups.com> wrote:
                             

                            This would be the first RISC-V chip developed by SiFive I believe.  SiFive was founded by the guys from Berkley who created the RISC-V.  I have been working with them on the RISC-V debug specification a little.

                            Ken

                            On 11/29/16 2:59 PM, spudarnia@... [nuttx] wrote:
                             

                            Yet another Crowd Supply RISC-V project: https://www.crowdsupply.com/ sifive/hifive1



                          • Ken Pettit
                            Developing an underpowered ASIC with a RISC-V and a couple of cores (i.e. underpowered because no FLASH, limited RAM, limited peripherals) really doesn t bring
                            Message 13 of 14 , Nov 29, 2016
                              Developing an underpowered ASIC with a RISC-V and a couple of cores (i.e. underpowered because no FLASH, limited RAM, limited peripherals) really doesn't bring anything to the table in terms of a usable finished product.  Seems like more of a test platform.  SiFive's business model is that they can provide RISC-V cores for integration into a larger ASIC, and the chip they developed is a test platform for demonstrating that capability I believe.  I'm not quite sure I understand SiFive's model for making money though ... I think it *might* be as a consulting firm to help companies develop custom extensions to the RISC-V ISA / core for specialized hardware acceleration, etc.

                              Ken

                              On 11/29/16 4:18 PM, franck gastel franckgastel@... [nuttx] wrote:
                               
                              again I do not get the goal of making an asic out of a risc + a couple of cores. what does it bring ?


                              On Wed, Nov 30, 2016 at 12:08 AM, Ken Pettit pettitkd@... [nuttx] <nuttx@yahoogroups.com> wrote:
                               

                              This would be the first RISC-V chip developed by SiFive I believe.  SiFive was founded by the guys from Berkley who created the RISC-V.  I have been working with them on the RISC-V debug specification a little.

                              Ken

                              On 11/29/16 2:59 PM, spudarnia@... [nuttx] wrote:
                               

                              Yet another Crowd Supply RISC-V project: https://www.crowdsupply.com/ sifive/hifive1




                            • Michael Smith
                              It proves you can do it. This can be interesting to other folks that might want you to do it for them as part of a larger effort. See e.g. PA Semi. = Mike
                              Message 14 of 14 , Nov 29, 2016
                                It proves you can do it. This can be interesting to other folks that might want you to do it for them as part of a larger effort.

                                See e.g. PA Semi.

                                 = Mike

                                On 29 Nov. 2016, at 4:18 pm, franck gastel franckgastel@... [nuttx] <nuttx@yahoogroups.com> wrote:


                                again I do not get the goal of making an asic out of a risc + a couple of cores. what does it bring ?


                                On Wed, Nov 30, 2016 at 12:08 AM, Ken Pettit pettitkd@... [nuttx] <nuttx@yahoogroups.com> wrote:
                                 

                                This would be the first RISC-V chip developed by SiFive I believe.  SiFive was founded by the guys from Berkley who created the RISC-V.  I have been working with them on the RISC-V debug specification a little.

                                Ken

                                On 11/29/16 2:59 PM, spudarnia@... [nuttx] wrote:
                                 

                                Yet another Crowd Supply RISC-V project: https://www.crowdsupply.com/ sifive/hifive1






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